One class of digital data communication protocols use data signals that carry both the data stream and a data clock on a single channel. In these protocols, the receiving circuit includes a clock and data recovery CDR circuit which produces a recovered clock, based typically on a local reference clock that has a frequency close to that of the clock carried in the data signals. The receiving circuit uses the recovered clock to set sampling times for sampling the data signals on the channel. Phase differences between the recovered clock and the data signals can be detected and used as feedback in the generation of the recovered clock.
One limitation on the data rate in communication channels is jitter tolerance, where jitter is variation in the relative timing of the sampling times, which can be generally characterized as phase of the local recovered clock, and transitions in the data signals that correlate with the ideal sampling times for the data signals. In CDR based systems, jitter can arise from a number of sources. For example, some variations in the data clock due to transmitter-side circuits can cause relatively low frequency jitter. Also, power supply noise on either the transmitter-side or the receiver-side can cause higher frequency jitter. The CDR sampling window, or data eye, is narrowed by poor jitter tracking, limiting the maximum data rate than can be achieved.
An object of the technology described herein is to provide a CDR circuit, and a method for clock recovery, achieving improved jitter tolerance.